1 idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) military and commercial temperature ranges january 2000 1999 integrated device technology, inc. dsc-5491/- c idt54/74fct374t/at/ct/dt military and commercial temperature ranges fast cmos octal d register (3-state) description: the fct374tis an 8-bit register built using an advanced dual metal cmos technology. these registers consist of eight d-type flip-flops with a buffered common clock and buffered 3-state output control. when the output enable ( oe ) input is low, the eight outputs are enabled. when the oe input is high, the outputs are in the high-impedance state. input data meeting the set-up and hold time requirements of the d inputs is transferred to the q outputs on the low-to-high transition of the clock input. d 0 q 0 d 1 q 1 d 2 q 2 d 3 q 3 d 4 q 4 d 5 q 5 d 6 q 6 d 7 q 7 cp oe d q cp d cp d cp d cp d cp d cp d cp d cp qqq q q qq functional block diagram features: - low input and output leakage 1 a (max.) - extended commercial range of C40c to +85c - cmos power levels - true ttl input and output compatibility v oh = 3.3v (typ.) v ol = 0.3v (typ.) - meets or exceeds jedec standard 18 specifications - product available in radiation tolerant and radiation enhanced versions - military product compliant to mil-std-883, class b and desc listed (dual marked) - available in dip, soic, ssop, qsop, tssop, cerpack, and lcc packages - std., a, c and d speed grades - high drive outputs (-15ma i oh , 48ma i ol )
2 military and commercial temperature ranges idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) pin configuration dip/ soic/ ssop/ qsop/ tssop/ cerpack top view note: 1. h = high voltage level l = low voltage level x = dont care z = high impedance nc = no change - - - - - = low-to-high transition 2 3 1 16 15 14 11 19 18 20 17 13 12 5 6 7 4 p20-1 d20-1 so20-2 so20-7 so20-8 so20-9 e20-1 8 9 10 d 1 q 0 d 0 v cc q 1 d 3 q 2 d 2 q 3 gnd q 7 q 6 d 7 d 6 q 5 q 4 d 5 d 4 cp oe 1 2 3 4 5 7 9 6 8 10 11 12 13 14 15 16 17 18 19 20 l20-2 q 6 d 7 d 6 q 5 d 5 d 0 q 0 q 3 gnd cp q 4 d 4 oe v cc q 7 index d 1 q 1 d 3 q 2 d 2 pin description pin names description d n d flip-flop data inputs cp clock pulse for the register. enters data on low-to- high transition. q n 3-state outputs (true) q n 3-state outputs (inverted) oe active low 3-state output enable input function table (1) inputs outputs internal function oe cp d n q n q n hi-z h h l h x x z z nc nc load register l l h h - - - - l h l h l h z z h l h l absolute maximum ratings (1) symbol rating max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C60 to +120 ma 8t-link notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. outputs and i/o terminals only. capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf 8t-link note: 1. this parameter is measured at characterization but not tested. lcc top view
3 idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) military and commercial temperature ranges notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at vcc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. the test limit for this parameter is 5 a at t a = C55c. symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 v v il input low level guaranteed logic low level 0.8 v i ih input high current (4) v cc = max. v i = 2.7v 1 a i il input low current (4) v i = 0.5v 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 i ozl (3-state output pins) (4) v o = 0.5v 1 i i input high current (4) v cc = max., v i = v cc (max.) 1 a v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v v h input hysteresis 200 mv i cc quiescent power supply current v cc = max., v in = gnd or v cc 0.01 1 ma 8t-link dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40c to +85c, v cc = 5.0v 5%; military: t a = C55c to +125c, v cc = 5.0v 10% output drive characteristics symbol parameter test conditions (1) min. typ. (2) max. unit v oh output high voltage v cc = min. v in = v ih or v il i oh = C6ma mil. i oh = C8ma coml 2.4 3.3 v i oh = C12ma mil. i oh = C15ma coml. 23 v ol output low voltage v cc = min. v in = v ih or v il i ol = 32ma mil. i ol = 48ma coml. 0.30.5 v i os short circuit current v cc = max., v o = gnd (3) C60 C120 C225 ma
4 military and commercial temperature ranges idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp/ 2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 2 ma i ccd dynamic power supply current (4) v cc = max. outputs open v in = v cc v in = gnd 0.15 0.25 ma/ mhz oe = gnd one input toggling 50% duty cycle i c total power supply current (6) v cc = max. outputs open v in = v cc v in = gnd 1.53.5ma f cp = 10mhz 50% duty cycle oe = gnd fi = 5mhz v in = 3.4 v in = gnd 25.5 50% duty cycle one bit toggling v cc = max. outputs open v in = v cc v in = gnd 3.87.3 (5) f cp = 10mhz 50% duty cycle oe = gnd eight bits toggling v in = 3.4 v in = gnd 6 16.3 (5) fi = 2.5mhz 50% duty cycle
5 idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) military and commercial temperature ranges notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. switching characteristics over operating range - commercial fct374t fct374at fct374ct fct374dt symbol parameter conditions (1) min . (2) max . min . (2) max . min . (2) max . min . (2) max . unit t plh t phl propagation delay cp to q n c l = 50pf r l = 500 w 2 10 2 6.5 2 5.2 2 4.2 ns t pzh t pzl output enable time 1.5 12.5 1.5 6.5 1.5 5.5 1.5 4.8 ns t phz t plz output disable time 1.5 8 1.5 5.5 1.5 5 1.5 4 ns t su set-up time high or low, d n to cp 2222ns t h hold time high or low, d n to cp 1.5 1.5 1.5 1 ns t w cp pulse width high or low (3) 7553ns switching characteristics over operating range - military fct374t fct374at fct374ct symbol parameter conditions (1) min . (2) max . min . (2) max . min . (2) max . unit t plh t phl propagation delay cp to q n c l = 50pf r l = 500 w 2 11 2 7.2 2 6.2 ns t pzh t pzl output enable time 1.5 14 1.5 7.5 1.5 6.2 ns t phz t plz output disable time 1.5 8 1.5 6.5 1.5 5.7 ns t su set-up time high or low, d n to cp 222ns t h hold time high or low, d n to cp 1.5 1.5 1.5 ns t w cp pulse width high or low (3) 766ns
6 military and commercial temperature ranges idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test cir cuits and w a veforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width switch position test switch open drain disable low closed enable low all other tests open 8-link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns
7 idt54/74fct374t/at/ct/dt fast cmos octal d register (3-state) military and commercial temperature ranges corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information 374t 374at 374ct 374dt octal d register p d so py q pg e l plastic dip (p20-1) cerdip (d20-1) small outline ic (so20-2) shrink small outline package (so20-7) quarter-size small outline package (so20-8) thin shrink small outline package (so20-9) cerpack (e20-1) leadless chip carrier (l20-1) xx temp. range xxxx device type x package x process blank b commercial mil-std-883, class b 74 54 - 40c to +8 5c - 55c to +1 25c idt fct
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